Rapid development of the integrated circuit technique greatly benefits from the continuous reduction of the length of the channel region of the field-effect device, and at present, the length of the channel region can be shortened to the level of deep submicron and even nanometer. However, a further reduction of the length of the channel region is limited by a number of factors, and this is due to the issues of the processing capacity and the device physical effects (e.g., the short channel region effects). Therefore, in order to improve the performances of the device and the circuit, and further exert the potential of the semiconductor material and the device structure, other technical measures which are more effective shall be taken.
Currently, a technical measure widely recognized as effective is focused on the improvement of the semiconductor carrier mobility. In the metal semiconductor Field Effect Transistor (FET), increasing the carrier mobility in the channel region and reducing the length of the channel region achieve similar effects, and both can greatly increase the device driving current, thereby improving the device working speed. In addition, increasing the carrier mobility is also required to improve the short channel region effects: when the length of the channel region is reduced to about 30 nm or less, a very strong electric field will be generated in the channel region, and under the strong electric field, the mobility decreases and the saturation current drops greatly. Therefore, it is important either for the common device or for the short channel device to increase the carrier mobility in the channel region.
It is known that the carrier mobility of the semiconductor material can be increased by applying a stress to the FET. When the stress is applied to the FET, the electron mobility can be increased by a tensile stress, and the hole mobility can be increased by a compressive stress. The technique of applying a press to the FET is referred to as stress engineering.
A Stress Memorization Technique (SMT) has been set forth to apply a stress to the channel region of the FET. Specifically, referring to FIG. 1, a transistor 100 is formed on a semiconductor substrate 102, and the transistor 100 comprises a gate 106, a gate dielectric layer 110, a gate spacer 112, a source/drain 108, a channel region 114 and a Shallow Trench Isolation (STI) structure 104. The surface of the transistor 100 is covered with a stress silicon nitride layer 116, so that the stress silicon nitride layer 116 applies a stress to the channel region 114. After that, the transistor is annealed so that the stress is memorized in the channel region 114, and then the stress silicon nitride layer 116 is removed.
The main problem of the above existing SMT method is that the nitride material only can provide a simplex tensile stress under the high temperature, thus the above method merely can generate a simplex tensile stress in the channel region. As a result, the existing SMT method can only be applied to the n-type FET, and is impossible to be applied to the p-type FET. Unfortunately, the performance of the p-type FET is generally a key to restrict the device performance. In silicon, the hole mobility is about 2.5 times less than the electron mobility, and thus in the integrated circuit, the maximum working frequency and speed are obviously more restricted by the performance of the p-type FET.
Therefore, a SMT method that can be applied to the p-type FET is required.